I think FPGA/ASIC recruiting pipelines are broken

I’m honestly sick of how FPGA interviews have turned into a coding exercise. I really don’t like the fact that recruiting for FPGA roles has turned into something that a simple keyword search can perform: Verilog and VHDL.

Am I insane for thinking this, but is RTL the easy part? Shipping a design that closes timing, survives temperature corners, and doesn’t implode under noisy conditions is where experience shows up.

When your design goes south, what do you even do? I find that lesser graduates now don’t know how to troubleshoot.

This keyword-first recruiting selects for folks who can write syntactically valid Verilog but can’t read a timing report when you’re under pressure to miss a deadline.

It’s truly sad, since this recruiting methodology misses candidates who’ve actually debugged CDC bugs that only show up once a week, tested in a temperature chamber, and learned that if something works in simulation, there’s a fine chance it doesn’t work in real life.

Here’s my message to recruiters: focus more on conceptual skills and troubleshooting scenarios instead of turning your interview into a Verilog Leetcode exam.

I see students and new grads asking for roadmaps and classes and why they can’t get jobs. Here’s my number one piece of advice: start working with people.

If you work with people on meaningful projects, you understand how others think and how to apply that to your own work. Working with people also means more meaningful outcomes and better resume material.

I don’t think there’s any excuse for interview mediocrity either. If creativity is required in your job, why are we not doing the same in our prep?

Getting reps has never been easier: hardware-interview forums, grind Voltage Learning prompts, Leetcode problem sets, interview copilots, or simply reading datasheets and app notes.

These Reddit posts asking “oh I have XYZ interview please give me answers” need to stop.

If you’ve never dealt with false paths, multicycle constraints, generated clocks, and IO timing, you’re basically doing FPGA in sandbox mode.

Please focus more on conceptual skills and stop turning ASIC, digital design, and FPGA interviews into a coding challenge.

Am I going crazy here, or does anyone else see it the same way?