Power Integrity, Signal Integrity, and Timing Hardware Interviews

Power integrity, signal integrity and timing interview questions all test the same skill: connecting a physical mechanism to a number and a measurement. A good answer names the mechanism (inductance limits how fast supply current can change, an impedance mismatch reflects part of a signal, a slow path misses the setup window). Then it puts a rough number on it and says how you'd confirm it on the bench. These topics are core to board-level, SI/PI, SoC and FPGA roles, and they interact: supply droop slows gates, and slower gates eat timing margin. Below you'll find practice questions with model answers and worked math, three scenario walkthroughs, and a five-step method for questions you haven't seen.

Everything here builds on RC circuits, LC resonance and impedance. If those feel rusty, review the circuit concepts every hardware engineer should know first.

PI, SI and Timing at a Glance

Each topic asks a different question about the same hardware. Use this table as a map for the rest of the guide.

Power Integrity Interview Questions

Power integrity questions ask why a supply droops and how you keep the droop inside budget. The core idea is that the power delivery network (PDN) has to look like a low impedance from DC up to the frequencies where the load current changes. Keysight's application note says reaching a target impedance across a broad frequency range takes "a power supply for the low frequencies" and "decoupling capacitors for the higher frequencies" (Keysight).

The questions below are practice questions of the kind asked in hardware interviews, not any specific company's questions. Numbers marked illustrative are made up to show the math.

What is target impedance, and how do you calculate it?

Target impedance is the highest PDN impedance that keeps the ripple inside budget for the worst current step. Keysight defines it as "a simple estimate using the maximum allowed ripple divided by the maximum expected current step load" (Keysight):

Z_target = ΔV_allowed / ΔI_step

Keysight's FPGA example uses 60 mV of allowed ripple and a 5 A step, which gives 12 mΩ.

Now an illustrative case: a 0.8 V core rail with 5% allowed ripple has a 40 mV budget. With a 10 A load step, the target is 40 mV / 10 A = 4 mΩ. Lower rail voltages and bigger current steps both push the target down.

A good follow-up point: it's an estimate. The PDN has to stay at or below that value across the whole band, so one resonant peak above it can still break the budget.

Why does a board use so many capacitor values and sizes?

A real capacitor is a series circuit of capacitance, equivalent series resistance (ESR) and equivalent series inductance (ESL). Murata explains self-resonance as "the series resonance occurring between Cap and ESL." At that self-resonant frequency (SRF), the impedance reaches its minimum and equals the ESR (Murata). Below the SRF the part acts like a capacitor. Above it, it acts like an inductor.

The SRF follows the standard series LC resonance:

f_SRF = 1 / (2π · √(L · C))

Illustrative numbers: a 100 nF capacitor with 0.5 nH of ESL resonates at about 22.5 MHz. But the part doesn't sit in free space. AMD's UltraScale PCB guide says the vias, traces and pads of a 2-terminal capacitor add "between 300 pH to 4 nH," typically about as much as or more than the capacitor's own inductance (AMD UG583). Add an illustrative 1 nH of mounting inductance and the total becomes 1.5 nH. The SRF drops to about 13 MHz.

That's why designs mix values. Large capacitors cover lower frequencies, and small, low-inductance parts close to the pins extend coverage higher. Two good follow-ups: placement can matter as much as value, and capacitors with different SRFs can form anti-resonant peaks between them.

Scenario: a chip resets or throws errors under heavy load. What do you check?

Start with the droop equation. It's a standard circuit relation:

V_droop ≈ I · R + L · di/dt

I·R is the DC drop through planes and package. L·di/dt is the fast droop when current changes quickly. Then walk through it:

1. Estimate the fast droop. Illustrative: a 10 A step in 10 ns is 1 A/ns. Through 0.1 nH of loop inductance (the effective value of many capacitors in parallel plus the planes), L·di/dt = 0.1 nH × 1 A/ns = 0.1 V. That's 100 mV, or 2.5 times the 40 mV budget from the example above.
2. Name what sets it. In that first fast droop, inductance often matters more than total capacitance, because the charge can't get from the capacitor to the die fast enough. AMD notes that "the current path's inductance is proportional to the loop area the current traverses" (AMD UG583). Small loops mean close capacitors, short connections and vias right at the pads.
3. Think in frequency. The regulator handles slow changes, board capacitors the middle range, and package and on-die capacitance the fastest edges. Ask where on the PDN impedance curve the load step lands.
4. Check shared returns. When many outputs switch at once, current through shared package ground inductance lifts the chip's internal ground. That's simultaneous switching noise, or ground bounce.
5. Measure it. Follow a structured debugging framework: probe at the chip, not the regulator, with a short ground and a 1:1 or rail probe. Trigger on the reset line and check whether the dip crosses the reset threshold.
6. Fix it. Cut loop inductance, add capacitance where the impedance peaks, tune regulator compensation, or stagger load turn-on.

How do you measure ripple and noise on a supply rail?

The probe setup can change the answer, so describe it before you quote a number. SiTime notes that a passive probe's ground wire "causes ringing, over- and undershoots and further increases rise time." In SiTime's oscillator-probing example, a standard ground lead with 16 pF of probe capacitance resonated at about 90 MHz. Their advice: "keep the area of a probe ground loop as small as possible" (SiTime).

Attenuation matters too. Rohde & Schwarz says a 10:1 passive probe adds measurement noise that overstates peak-to-peak voltage. On the same 1.5 V rail, they measured 50 mV peak-to-peak with a 10:1 passive probe and 31.8 mV with a 1:1 passive probe (Rohde & Schwarz). The catch: 1:1 passive probes are limited to bandwidths in the tens of MHz, which is why active rail probes exist. A complete answer: spring ground tip at the load, low attenuation, enough bandwidth, and a capture during the worst-case load step.

Signal Integrity Interview Questions

Signal integrity questions test whether you know when a trace stops acting like a wire. Once an edge is fast compared with the trace's delay, the signal travels as a wave, and every change in impedance reflects part of it.

What is the reflection coefficient, and what does it tell you?

The reflection coefficient is the fraction of an incident voltage wave that bounces back at a load (Ellingson, Virginia Tech):

Γ = (ZL - Z0) / (ZL + Z0)

Work the standard cases:

• 50 Ω line into 75 Ω: Γ = 25 / 125 = 0.2. Twenty percent of the incident step reflects with the same polarity. For an illustrative 1 V step, the load briefly sees 1.2 V.
• 50 Ω line into 25 Ω: Γ = -25 / 75 ≈ -0.33. The reflection is inverted, and the load sees about 0.67 V.
• Matched load: Γ = 0, no reflection.
• Open: Γ = +1, the voltage doubles.
• Short: Γ = -1, the voltage at the load is zero.

When does a PCB trace need to be treated as a transmission line?

Use a rule of thumb, and say it's one. LearnEMC says transmission-line analysis is generally needed when signal transition times "are less than twice the propagation delay" (LearnEMC). Note that edge rate sets this, not clock frequency.

To put a number on it, estimate the delay per inch from t_pd = √εr / c. Light takes about 85 ps per inch in free space. With an illustrative εr of about 4 for FR-4, t_pd ≈ 2 × 85 = 170 ps/in. That's approximate: microstrip runs a bit faster, because part of its field is in air.

With an illustrative 1 ns edge, the rule says to treat the trace as a transmission line once its delay exceeds 0.5 ns. That's about 500 / 170 ≈ 3 inches. Other sources use stricter fractions, so mention that the boundary is fuzzy.

Scenario: a serial link works at a low data rate but fails at a higher one. Why?

Three things get worse together as the rate goes up:

1. The unit interval shrinks. UI = 1 / bit rate. Illustrative: 1 Gb/s gives a 1 ns UI, and 10 Gb/s gives 100 ps. The same ringing and jitter now eat a much larger share of each bit.
2. Channel loss grows with frequency. Conductor and dielectric losses rise as frequency goes up, so edges smear. Each bit's tail spills into the next one. That's intersymbol interference (ISI).
3. Faster edges see smaller discontinuities. Vias, connector pins, pads and stubs that were invisible at slow edges now reflect. Reflections that settled within a long UI now land on the next bit.

Then say how you'd check it. Run a TDR on the channel to find impedance discontinuities. Capture an eye diagram at both rates and compare the openings. Look at the layout for reference-plane gaps or layer changes that break the return path. Fixes include matching impedance, removing stubs, adding or tuning equalization, and choosing a lower-loss channel.

If the role touches RF or very high-speed channels, expect S-parameter follow-ups. The RF engineering interview tips cover that side.

How do TDR and eye diagrams help you debug?

A TDR shows where the impedance changes. Keysight describes it simply: "The TDR module launches a fast voltage incident step (Ei) into the DUT," and the reflected wave adds to the incident one on screen. The ratio of reflected to incident voltage is the reflection coefficient ρ, and knowing both "allows ZL to be determined" (Keysight FlexDCA).

Rearranging the Γ formula gives ZL = Z0 · (1 + ρ) / (1 - ρ). A reading of ρ = 0.2 on a 50 Ω system means 50 × 1.2 / 0.8 = 75 Ω. The timing of each bump gives its location (half the round-trip time, times the propagation velocity).

An eye diagram overlays many bits. Eye height is the vertical opening, your voltage margin. Eye width is the horizontal opening, your timing margin after jitter and ISI.

Series vs parallel termination: when do you use each?

Termination stops reflections by giving the wave a matched impedance at one end.

• Series (source) termination: add a resistor at the driver so driver impedance plus resistor equals Z0. The driver launches a half-amplitude wave. It reflects off the high-impedance receiver (Γ near +1) and doubles to full swing, then gets absorbed at the matched source. It draws no DC current. It suits point-to-point links, but a load in the middle of the line sees a half-height step for a moment.
• Parallel (end) termination: put a resistor equal to Z0 at the receiver, to ground or to a termination voltage. The wave is absorbed on the first pass, so every point sees full swing. The cost is DC power.

Differential pairs usually get a resistor across the pair matched to the differential impedance. The receiver reads the difference between the two lines, so noise common to both mostly cancels. Keep the pair matched in length and over a solid reference plane: high-frequency return current flows in the plane right under a trace, and a gap forces it through a larger loop.

Setup and Hold Timing Interview Questions

Timing questions check whether you can write the setup and hold checks from memory and say what moves each one.

How do you write the setup and hold constraints for a register-to-register path?

MIT's 6.111 tutorial states the two checks plainly: "tPD + tS <= tCLK" for setup and "tH <= tCD" for hold (MIT 6.111). Here tPD is the slowest path delay (clock-to-Q plus logic), and tCD is the fastest one, the contamination delay.

Their worked example uses a 25 ns clock, a register with a 6 ns clock-to-Q delay, and a slowest logic path of 11 ns. The largest setup time the next register can have is 25 - 6 - 11 = 8 ns. For hold, a 2 ns minimum register delay plus a 4 ns minimum logic delay allows a hold time of up to 6 ns.

How do you calculate setup slack with clock skew and uncertainty?

Real tools add skew and clock uncertainty. AMD's UltraFast methodology guide gives (AMD UG949):

Setup slack = requirement - max data path delay + clock skew - clock uncertainty - setup time

Clock skew there is "destination clock delay - source clock delay." Clock uncertainty is "the total amount of possible time variation between any pair of clock edges," and it includes clock jitter (AMD UG906).

Illustrative 1 GHz example:

• Requirement (clock period): 1000 ps
• Max data path: 80 ps clock-to-Q + 750 ps logic = 830 ps
• Skew: +20 ps (capture clock arrives later)
• Uncertainty: 50 ps
• Setup time: 50 ps

Setup slack = 1000 - 830 + 20 - 50 - 50 = 90 ps. Positive slack means the path passes.

How do you calculate hold slack, and why can't a slower clock fix it?

UG949's hold equation is:

Hold slack = requirement + min data path delay - clock skew - clock uncertainty - hold time

Illustrative example: a min path of 60 ps clock-to-Q plus 50 ps logic gives 110 ps. With a hold requirement of 0 (same-edge check), 20 ps of skew, 30 ps of uncertainty and a 40 ps hold time:

Hold slack = 0 + 110 - 20 - 30 - 40 = 20 ps.

Look at what's missing: the clock period. For a standard single-cycle path, the hold check compares the same clock edge at launch and capture, so the frequency never appears. That matches MIT's tH <= tCD. Slowing the clock gives setup more room but does nothing for hold. The exceptions are paths between opposite clock edges and multicycle paths, where the hold requirement depends on the period.

Corners matter here. AMD defines the fast corner as "the highest voltage, and the lowest temperature," and the slow corner as "the lowest voltage, and the highest temperature." Vivado runs setup and hold at both by default (AMD UG835). Short paths get shortest at the fast corner, so hold margin is usually tightest there.

How do clock skew and jitter change the picture?

Skew helps one check and hurts the other. In the equations above, positive skew adds to setup slack and subtracts from hold slack. Designers sometimes use that on purpose to borrow time for a slow path, but the hold check on the same path pays for it.

Jitter shows up as clock uncertainty, which is subtracted in both equations. Noisy clock sources or noisy supplies on clock buffers make it worse.

How do you fix setup and hold violations?

What is metastability, and how do you cross clock domains safely?

If a flip-flop's input changes inside its setup and hold window, the output can hang between 0 and 1 for an unbounded time before it settles. That's metastability. It can't be eliminated, only made unlikely, because the chance of still being unresolved drops quickly with the time you allow.

For a single bit crossing into a new clock domain, use a two-flop synchronizer, fed straight from a flop in the source domain so no combinational glitch reaches it. The first flop may go metastable, and it gets a full cycle to settle before the second flop samples it. For multi-bit values, don't synchronize each bit separately, because the bits can land on different cycles. Use Gray-coded counters, a handshake, or an asynchronous FIFO. A short pulse from a fast domain can be missed entirely by a slow one, so stretch it or use a handshake. For more on how chip teams probe this area, see these ASIC design interview tips.

When All Three Collide: Passes Simulation, Fails in the Lab

When a design passes timing checks but fails in the lab only under heavy switching, suspect the supply first. Heavy activity draws large current steps, the rail droops, and lower voltage moves the chip toward the slow corner, which AMD defines as lowest voltage and highest temperature (AMD UG835). Slower gates shrink setup slack. Supply noise can also add clock jitter beyond what the clock-uncertainty constraint assumed. Static timing assumed conditions the board didn't deliver at that moment.

Walk through it in order:

1. Clarify "simulation." RTL simulation usually has no real delays. Ask whether static timing passed with complete constraints. Missing constraints and unconstrained clock-domain crossings often explain a design that passes in software and fails on hardware.
2. Confirm it depends on activity. Does it fail only under the heaviest workload, or get worse when hot? On most processes, both point toward slower delays.
3. Lower the clock frequency. If the failure goes away, it behaves like a setup problem. Same-edge hold failures don't care, because that check has no tCLK in it. A slower clock also cuts current draw and droop, so pair this with the voltage test in step 4.
4. Margin the supply within datasheet limits. If raising the voltage helps and lowering it hurts, it's a speed problem. Hold problems tend to do the opposite, since higher voltage makes short paths faster.
5. Probe the rail during the failure. Trigger on an error flag or debug pin and check whether the droop lines up with the errors.
6. Check the clock. See whether jitter grows under load.
7. Fix the cause. Improve the PDN, add margin in the constraints, fix the crossing, or lower the frequency if the product allows it.

The hardware engineering debugging interview guide shows how to present a debug story like this one.

A 5-Step Way to Answer Any PI, SI or Timing Question

When you get a question you haven't seen, run the same five steps out loud:

1. Pin down the symptom. What fails, when, and under which conditions (load, rate, temperature, voltage)?
2. Name the mechanism in one sentence. For example: "Fast current steps through loop inductance cause droop," or "Faster edges reflect off the via stub."
3. Write the equation and put a rough number on it. Say your assumptions, and call illustrative numbers illustrative.
4. Say how you'd confirm it. Name the instrument, the setup, and the result that would rule your idea out.
5. Propose fixes and their cost. Board area, power, latency, parts count or schedule.

Steps 3 and 4 are what turn a definition into an engineering answer. Practicing on a whiteboard helps, and this whiteboard interview guide for hardware engineers shows how to lay the work out clearly.

Common Mistakes That Weaken Good Answers

Each of these turns a correct idea into a weak answer:

• Defining without a mechanism. "Signal integrity is signal quality" explains nothing. Say what physically degrades it.
• "Add more capacitors." Without a frequency band and mounting inductance, this stops at the first follow-up.
• Using clock frequency to decide if a trace is a transmission line. Edge rate decides it.
• Getting the skew sign backwards. Positive skew (later capture clock) helps setup and hurts hold.
• Trusting a rail measured with a long ground lead. The probe adds its own ringing.
• Jumping to a fix before a measurement. Say what you'd measure first.

How to Prepare, Plus a Checklist

Weight your prep by role. Board-level, SI/PI and high-speed interface roles lean on the PDN and transmission-line material. SoC, ASIC and FPGA roles lean on timing and clock-domain crossings. System-level interviews mix all three, and these hardware system design interview questions show how they come up in a bigger design.

Before your interview, make sure you can do each of these without notes:

1. Define target impedance and compute an example from a ripple budget and a current step.
2. Draw a real capacitor's model, compute an SRF, and explain mounting inductance.
3. Estimate L·di/dt droop and say why inductance often sets the fast droop.
4. Compute Γ for matched, open, shorted and one mismatched load.
5. State the transmission-line rule of thumb and derive delay per inch from εr.
6. Explain series vs parallel termination and when each fits.
7. Write the setup and hold slack equations with the skew sign right.
8. Explain why a same-edge hold check doesn't depend on clock frequency, and name the exceptions.
9. Sketch a two-flop synchronizer and say when it isn't enough.
10. Describe how you'd probe a rail, read a TDR trace and judge an eye diagram.
11. Talk through all three scenarios above using the five-step method.

Then practice out loud. Work through a bank of hardware interview questions, and use the hardware engineering practice exercises to drill one topic at a time.