When EE interviews become “draw a circuit, panic quietly” … here are 4 ways to not do that.

I used to think I was bad at interviews until I sat on the other side of the table. Since then, I’ve watched a lot of electrical engineers walk into interviews like it’s a pop quiz plus coupled with interpretive dance. They sit down, fumble through the resume walk, calculate voltage dividers incorrectly, and proceed to spend 15 minutes remembering what an XOR gate is.

I personally don’t think interviewing is fully reinventing the wheel. Here are tactics that make you look like a real EE, even when your brain does the Windows shutdown sound.

Circuit design: don’t be an artist

When I ask “design an amplifier / filter / regulator,” don’t start sketching like you’re doing your best Michelangelo interpretation. This is what I’m looking for, start with three questions (example): What are the input and output ranges? What is the load? What is the noise, bandwidth, or ripple target?

Moral of the story: Asking questions before shows that you adapt to real world considerations. It shows thought processes and what you would do when a situation like this presents itself.

Block diagramming: KISS philosophy

I should’ve written this point before the previous because circuit diagrams are overrated. A lot of EEs lose points because they jump straight into details. You know who doesn’t jump into deep end, actual engineers when they design systems. Draw a clean block diagram first, even if they asked for a circuit. Start with source, conditioning, conversion, processing, output. Label domains: analog, digital, power. Keep it simple guys, no need to start doing logic reduction immediately.

Communication: Intentionally overdo it

Talk… that’s it. Say everything, think everything, and then say it again. Bonus points for using a consistent structure. It keeps you from rambling and it makes the interviewer’s notes easy. Silence doesn’t mean that you’re thinking hard, it means that your eyes have glazed over.

Interview topics: Does anyone read the JD?

This is by far the most mind-boggling thing. If it’s an analog role, there’s going to be circuit design. If it’s an ASIC design role, there will likely be RTL, logic design, floorplanning. Read the JD and you get literally everything that they’re asking for. In fact it so easy that I have my very own EE technical interview resource with topics and exercises linked within my profile. No road map necessary (or allowed). In fact, I’ll be willing to bet that interview topics haven’t drastically changed in like 5 years, since we’re all technically doing the same nonsense.

Ok finally real talk… interviewers are human. Sometimes tired, sometimes under pressure, sometimes with tight deadlines. Yet, it’s nonnegotiable to make yourself seem like a likable human being who is good to be around for 8+ hours every day in a windowless office.